ST ST8500 programmable power line communication (P

ST公司的ST8500可编动力线通信(PLC)调制解调器系统片上系统(SoC),能在频率高达500kHz运行任一种PLC协议.器件架构设计用于CENELEC EN50065, FCC和ARIB兼容的应用兵,支持所有主要的PLC标准如ITU G.9904(PRIME),ITU G.9903 (G3-PLC®)以及其它PLC协议规范和演进.器件包括具有自动增益控制的PGA和ADC,具有发送预驱动器的DAC,数字发送电平控制,以及零交叉比较器.高达500kHz的PLC信号带宽. ST8500具有标准32位ARM® Cortex-M4FMCU可编核,用于协议上层和外设管理,最大工作频率200MHz,嵌入用于代码和数据256kB的SRAM,嵌入96kB数据SRAM,8kB共享RAM和引导ROM存储器.外接3.3V用于I/O和模拟电源,2.5V内部线性稳压器用于模拟,1.1V外接电源用于数字,具有正常,慢,打盹和低功耗模式,采用QFN56封装,工作温度-40℃ 到 +105℃.主要用于智能计量,智能电网和物联网(IoT),以及CENELEC, FCC与ARIB兼容的应用设计.本文介绍了ST8500主要特性,基本框图和详细架构图,时钟树和电源方案,以及评估板EVALKITST8500-1主要特性,框图和电路图.

Programmable power line communication modem System on Chip evaluation kit The ST8500 is a fully programmable power line communication (PLC) modem System on Chip (SoC), able to run any PLC protocol in the frequency band up to 500 kHz.

The device architecture has been designed to target CENELEC EN50065, FCC and ARIB compliant applications supporting all major PLC protocol standards such as ITU G.9904(PRIME), ITU G.9903 (G3-PLC®) and many other possible PLC protocol specifications andevolutions.

ST8500主要特性:

 Programmable power line communication(PLC) modem System on Chip
 Integrated differential PLC analog front-end
– PGA with automatic gain control and ADC
– DAC with transmission pre-driver
– Digital transmission level control
– Zero crossing comparator
– Up to 500 kHz PLC signal bandwidth
 High performance, fully programmable realtimeengine dedicated to PLC PHY and real -time MAC protocol management (400 MHzmax. frequency)
– Dedicated code and data SRAM memories
 Standard ARM® 32-bit Cortex®-M4F fullyprogrammable core for protocol upper layers
and peripherals management
– 200 MHz maximum frequency
– 256 kB of embedded SRAM for code anddata
– 96 kB of embedded SRAM for data
– 8 kB of embedded shared RAM
– Bootloader ROM memory
– One Time Programmable (OTP) memorywith dedicated areas available for secure
keys and user information storage
– Serial wire and JTAG interfaces
– 24 multiplexed GPIOs
– 4 general purpose timers
– 1 flexible CRC calculation unit
– 2 USART, 1 UART, 3 SPI, 1 I2C
 Cryptographic engine
– AES 128/192/256 engine
– True random number generator
– Pseudo random number generator
 Clock management:
– 25 MHz external crystal for system clock
– Integrated 25 MHz oscillator (XOSC) withfrequency synthesizer (FS) and pre-scaler
units to generate internal clock signals
 Power management
– 3.3 V external supply voltage for I/O andanalog
– 2.5 V internal linear regulator for analog
– 1.1 V external supply voltage for digital
– Normal, Slow, Doze and low power modes
 Available in QFN56 package
 -40℃ to +105℃ temperature range

ST8500应用:

 Smart metering, smart grid and Internet ofThings applications
 Suitable for application design compliant withCENELEC, FCC and ARIB regulations
The ST8500 architecture is composed of the following parts:
1. PLC front-end including digital front-end (DFE) and analog front-end (AFE)
2. Real-time engine: the digital core running the lower layers of the PLC protocol stack
and implementing modulation, demodulation and advanced forward error corrections(FEC) algorithms
3. Protocol engine: the digital core running the upper layers of the PLC protocol stack and
managing the interface with external microcontrollers.
4. Peripherals, crypto, debug section
5. Clock and reset section
6. Power management section

图1.ST8500基本框图

图2.ST8500详细架构图

图3.ST8500时钟树图

图4.ST8500电源方案图

评估板EVALKITST8500-1

The EVALKITST8500-1 is a platform which allows an easy way to evaluate the features andperformance of a power line communication (PLC) node based on the ST8500 modemsystem-on-chip and the STLD1 line driver.

This user manual explains the EVALKITST8500-1 hardware and software installation, and
details the evaluation of the kits.

This user manual does not explain the functionalities of the various PLC protocols running
on the ST8500. Detailed information can be found in the protocol specific documentation,
available within the software packages, separately delivered under the Software license
agreement by contacting your local ST sales office.

Based on the ST8500 power line communication System on Chip, the EVALKITST8500-1 evaluation kit embeds all the functions required for a turnkey power line communication network.

Depending on the PLC protocol targeted, different firmware releases should be loaded on the host Flash memory. Please check software release availability with your local STMicroelectronics sales office.

Intuitive graphical user interface (GUI) for the Windows^® environment allows the user to upgrade the firmware release, configure and control the evaluation kit.

图5.评估板EVALKITST8500-1外形图

图6.评估板EVALKITST8500-1框图

图7.STM32控制板外形图

图8.STM32控制板概况图

图9.ST8500模块外形图

图10.ST8500模块概况图

图11.评估板EVALKITST8500-1电路图:EVALST-PLCMB1(1)

图12.评估板EVALKITST8500-1电路图:EVALST-PLCMB1(2)

图13.评估板EVALKITST8500-1电路图:PSU_VIPER板

图14.评估板EVALKITST8500-1电路图:ST8500模块板(1)

图15.评估板EVALKITST8500-1电路图:ST8500模块板(2)
详情请见:
https://www.st.com/content/ccc/resource/technical/document/user_manual/group0/3a/dc/89/3e
/4d/6d/46/d1/DM00467734/files/DM00467734.pdf/jcr:content/translations/en.DM00467734.pdf
st8500.pdf
en.DM00467734.pdf